(1) Field of the Invention
The present invention generally relates to dynamic random access memory devices, and more particularly to an improvement in a data read system thereof. More specifically, the present invention is concerned with a circuit for amplifying data read out to a pair of data bus lines from a memory cell via a pair of bit lines.
(2) Description of the Related Art
Recently, a current-mirror circuit has been used as an amplifier for amplifying data read out to a pair of data bus lines in order to rapidly read out data from a memory cell via a pair of bit lines and send the data to a circuit of the next stage.
FIG. 1 shows a current-mirror circuit 2 for amplifying data read out to a pair of data bus lines DB and DB and peripheral circuits thereof in a dynamic random access memory device. Data stored in a memory cell 1a or 1b is read out to the pair of data bus lines DB and DB when a word line WL1 or WL2 is switched to a high level and a column select signal C1 applied to gates of transistors Tr16 and Tr17 is switched to a high level. The readout data is applied, as complementary input signals IN and IN, to the current mirror circuit 2.
As shown in FIG. 1, the current mirror circuit 2 is composed of two P-channel field effect transistors Tr11 and Tr12, and three N-channel field effect transistors Tr13, Tr14 and Tr15. These field effect transistors are, for example, MOS transistors. The current mirror operation is realized by the transistors Tr11-Tr14. The input signals IN and IN are applied to the gates of the transistors Tr13 and Tr14, respectively. While an enable signal C2 is being applied to the gate of the transistor Tr15, the current mirror amplifier 2 amplifies the input signals IN and IN, and generates complementary output signals OUT and OUT via the drains of the transistors Tr13 and Tr14.
An N-channel field effect transistor Tr1 is connected between a high-potential power supply line Vcc and the data bus line DB, and an N-channel field effect transistor Tr2 is connected between the power supply line Vcc and the data bus line DB. The transistors Tr1 and Tr2 form an amplitude limiting circuit 3. The gates of the transistors Tr1 and Tr2 are connected to the Vcc line, so that the transistors Tr1 and Tr2 are always ON.
A description will now be given of the operation of the circuit shown in FIG. 1 with reference to FIG. 2A. While no complementary input signals are read out to the data bus lines DB and DB, the potentials of the data buses DB and DB, that is, the input signals IN and IN are maintained at a potential equal to Vcc-VthN where VthN is a threshold voltage of each of the transistors Tr1 and Tr2. For example, when Vcc=5 V and VthN.apprxeq.1 V, the input signals IN and IN are maintained at approximately 4 V.
In this state, when the word line WL1 or WL2 becomes the high level and the column select signal C1 becomes the high level, data read out to a pair of bit lines BL and BL from the selected memory cell 1a or 1b is sensed and amplified by a sense amplifier SA. Then, amplified data is transferred to the data bus DB and DB, so that the potential of the input signal IN on the low-level side decreases slightly. Meanwhile the input signal IN is not significantly changed, as shown in FIG. 2A.
When the enable signal C2 is input to the current mirror circuit 2, it pulls an output signal OUT up to a potential near the voltage Vcc and pulls an output signal OUT down to a potential nearly equal to zero volt on the basis of the potentials of the input signals IN and IN. In this way, the readout data on the pair of data bus lines DB and DB is amplified, and output, as the complementary output signals OUT and OUT, to a circuit of the next stage.
As indicated by a curve S shown in FIG. 2B, the current mirror circuit 2 operates most rapidly when the input signals are approximately equal to half the power supply voltage Vcc supplied to the current mirror circuit 2. Meanwhile, as indicated by a curve G shown in FIG. 2B, the current mirror circuit 2 has a maximum gain when the input signals IN and IN are lower than Vcc/2.
As has been described previously, the input signals IN and IN are maintained at (Vcc-VthN) equal to, for example, 4V, which is much higher than Vcc/2. In this state, the current mirror circuit 2 does not operate rapidly and does not have a large gain, as shown in FIG. 2B. Thus, the ability of the current mirror circuit 2 is not utilized completely. The current mirror circuit 2 has another disadvantage in that it stops the amplifying operation when the power supply voltage Vcc decreases momentarily due to noise and the input signals IN and IN momentarily become higher than the power supply voltage Vcc. In this case, it takes a long time for the current mirror circuit 2 to return to the normal amplifying operation after the power supply voltage Vcc returns to the normal level. Thus, the current mirror circuit 2 does not operate rapidly.